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ds554 (v1.2) june 9, 2009 www.xilinx.com product specification 1 ? 2006?2009 xilinx, inc. xilinx, the xilinx logo, virtex, spartan, ise, and other designated brands included herein are tradema rks of xilinx in the united states and other countries. all other trademarks are the property of their respective owners. features ? aec-q100 device qualification and full ppap support available in both i-grade and extended temperature q-grade ? guaranteed to meet full electrical specifications over t a = ?40c to +105c with t j maximum = +125c (q-grade) ? optimized for 1.8v systems ? industry?s best 0.18 micron cmos cpld - optimized architecture fo r effective logic synthesis - multi-voltage i/o operation ? 1.5v to 3.3v ? available in the following package options - 100-pin vqfp with 80 user i/o - 132-ball cp (0.5 mm) bga with 100 user i/o - pb-free only for all packages ? advanced system features - fastest in system programming 1.8v isp using ieee 1532 (jtag) interface - ieee1149.1 jtag boundary scan test - optional schmitt-trigger input (per pin) - unsurpassed low power management datagate enable (dge) signal control - two separate i/o banks - realdigital 100% cmos product term generation - flexible clocking modes optional dualedge triggered registers clock divider (divide by 2,4,6,8,10,12,14,16) coolclock - global signal options with macrocell control multiple global clocks with phase selection per macrocell multiple global output enables global set/reset - advanced design security - open-drain output option for wired-or and led drive - pla architecture superior pinout retention 100% product term routability across function block - optional bus-hold, 3-state or weak pull-up on selected i/o pins - optional configurable grounds on unused i/os - mixed i/o voltages compatible with 1.5v, 1.8v, 2.5v, and 3.3v logic levels - hot pluggable refer to the coolrunner?-ii automotive cpld family data sheet for architecture description. warning: programming temperature range of t a = 0 c to +70 c. description the coolrunner-ii automotive 128-macrocell device is designed for both high performance and low power applica- tions. this lends power savings to high-end communication equipment and high speed to battery operated devices. due to the low power stand-by and dynamic operation, overall system reliability is improved. this device consists of eight function blocks inter-con- nected by a low power advanced interconnect matrix (aim). the aim feeds 40 true and complement inputs to each function block. the function blocks consist of a 40 by 56 p-term pla and 16 macrocells which contain numerous configuration bits that allow for combinational or registered modes of operation. additionally, these registers can be globally reset or preset and configured as a d or t flip-flop or as a d latch. there are also multiple clock signals, both global and local product term types, configured on a per macrocell basis. output pin configurations include slew rate limit, bus hold, pull-up, open drain and programmable grounds. a schmitt-trigger input is available on a per input pin basis. in addition to stor- ing macrocell output states, the macrocell registers may be configured as direct input registers to store signals directly from input pins. clocking is available on a global or function block basis. three global clocks are available for all function blocks as a synchronous clock source. macrocell registers can be indi- vidually configured to power up to the zero or one state. a global set/reset cont rol line is also available to asynchro- nously set or reset selected registers during operation. additional local clock, synchronous clock-enable, asynchro- nous set/reset and output enable signals can be formed using product terms on a per-macrocell or per-function block basis. a dualedge flip-flop feature is also available on a per mac- rocell basis. this feature allows high performance synchro- nous operation based on lower frequency clocking to help reduce the total power consumption of the device. circuitry has also been included to divide one externally supplied global clock (gck2) by eight different selections. this yields divide by even and odd clock frequencies. 0 xa2c128 coolrunner-ii automotive cpld ds554 (v1.2) june 9, 2009 00 product specification r
xa2c128 coolrunner-ii automotive cpld ds554 (v1.2) june 9, 2009 www.xilinx.com product specification 2 r the use of the clock divide (division by 2) and dualedge flip-flop gives the resultant coolclock feature. datagate is a method to sele ctively disable inputs of the cpld that are not of interest during certain points in time. by mapping a signal to the datagate function, lower power can be achieved due to reduction in signal switching. another feature that eases voltage translation is i/o bank- ing. two i/o banks are available on the coolrunner-ii auto- motive 128-macrocell device that permit easy interfacing to 3.3v, 2.5v, 1.8v, and 1.5v devices. the coolrunner-ii automotive 128-macrocell cpld is i/o compatible with various jedec i/o standards (see ta bl e 1 ). this device is also 1.5v i/o compatible with the use of schmitt-trigger inputs. realdigital design technology xilinx coolrunner-ii automotive cplds are fabricated on a 0.18 micron process technology which is derived from lead- ing edge fpga product development. coolrunner-ii auto- motive cplds employ realdig ital technology, a design technique that makes use of cmos technology in both the fabrication and design methodology. realdigital technology employs a cascade of cmos gates to implement sum of products instead of traditional sense amplifier methodology. due to this technology, x ilinx coolrunner-ii automotive cplds achieve both high-performance and low power oper- ation. supported i/o standards the coolrunner-ii automotive 128-macrocell device fea- tures lvcmos and lvttl i/o implementations. see ta b l e 1 for i/o standard voltages. the lvttl i/o standard is a general purpose eia/jedec standard for 3.3v applica- tions that use an lvttl input buffer and push-pull output buffer. the lvcmos standard is used in 3.3v, 2.5v, 1.8v applications. ta b l e 1 : i/o standards for xa2c128 iostandard attribute output v ccio input v ccio lvttl 3.3 3.3 lvcmos33 3.3 3.3 lvcmos25 2.5 2.5 lvcmos18 1.8 1.8 lv c m o s 1 5 (1) 1.5 1.5 notes: 1. lvcmos15 requires use of schmitt-trigger inputs. figure 1: i cc vs frequency ta bl e 2 : i cc vs frequency (lvcmos 1.8v t a = 25c) (1) frequency (mhz) 0 255075100150 typical i cc (ma) 0.019 3.97 7.95 11.92 15.89 23.83 notes: 1. 16-bit up/down, resetable binary c ounter (one counter per function block). fre qu ency (mhz) d s 554_01_052109 i cc (ma) 0 150 100 50 20 0 10
xa2c128 coolrunner-ii automotive cpld ds554 (v1.2) june 9, 2009 www.xilinx.com product specification 3 r recommended operating conditions dc electrical characteristics (over recommended operating conditions) absolute maximum ratings symbol description value units v cc supply voltage relative to ground ?0.5 to 2.0 v v ccio supply voltage for output drivers ?0.5 to 4.0 v v jtag (2) jtag input voltage limits ?0.5 to 4.0 v v ccaux jtag input supply voltage ?0.5 to 4.0 v v in (1) input voltage relative to ground ?0.5 to 4.0 v v ts (1) voltage applied to 3-state output ?0.5 to 4.0 v t stg (3) storage temperature (ambient) ?65 to +150 c t j junction temperature +125 c notes: 1. maximum dc undershoot below gnd must be li mited to either 0.5v or 10 ma, whichever is easiest to achieve. during transitions, the device pins may undershoot to ?2.0v or overshoot to +4.5v, pr ovided this over or undershoot lasts less than 10 ns and with t he forcing current being limited to 200 ma. 2. valid over commercial temperature range. 3. for soldering guidelines and thermal considerations, see the device package user guide . for pb-free packages, see xapp427 . symbol parameter min max units v cc supply voltage for internal logic and input buffers industrial t a = ?40c to +85c 1.7 1.9 v q-grade t a = ?40c to +105c t j maximum = +125c 1.7 1.9 v v ccio supply voltage for output drivers @ 3.3v operation 3.0 3.6 v supply voltage for output drivers @ 2.5v operation 2.3 2.7 v supply voltage for output drivers @ 1.8v operation 1.7 1.9 v supply voltage for output drivers @ 1.5v operation 1.4 1.6 v v ccaux supply voltage for jtag programming 1.7 3.6 v symbol parameter test conditions typical max. units i ccsb standby current industrial v cc = 1.9v, v ccio = 3.6v 60 200 a i ccsb standby current q-grade v cc = 1.9v, v ccio = 3.6v 60 1.5 ma i cc (1) dynamic current f = 1 mhz - 2.0 ma f = 50 mhz - 12 ma c jtag jtag input capacitance f = 1 mhz - 10 pf c clk global clock input capacitance f = 1 mhz - 12 pf c io i/o capacitance f = 1 mhz - 10 pf i il (2) input leakage current v in = 0v or v ccio to 3.9v - 10 a i ih (2) i/o high-z leakage v in = 0v or v ccio to 3.9v - 10 a notes: 1. 16-bit up/down, resetable binary c ounter (one counter per function block).
xa2c128 coolrunner-ii automotive cpld ds554 (v1.2) june 9, 2009 www.xilinx.com product specification 4 r lvcmos and lvttl 3.3v dc voltage specifications lvcmos 2.5v dc voltage specifications 1. the v ih max value represents the jedec specification for lvcmos25. the coolrunner-ii input buffer can tolerate up to 3.9v without physical damage. symbol parameter test conditions min. max. units v ccio input source voltage 3.0 3.6 v v ih high level input voltage 2.0 3.9 v v il low level input voltage ?0.3 0.8 v v oh high level output voltage, industrial grade i oh = ?8 ma, v ccio = 3v v ccio ? 0.4v - v i oh = ?0.1 ma, v ccio = 3v v ccio ? 0.2v - v high level output voltage, q-grade i oh = ?4 ma, v ccio = 3v v ccio ? 0.4v - v i oh = ?0.1 ma, v ccio = 3v v ccio ? 0.2v - v v ol low level output voltage, industrial grade i ol = 8 ma, v ccio = 3v - 0.4 v i ol = 0.1 ma, v ccio = 3v - 0.2 v low level output voltage, q-grade i ol = 4 ma, v ccio = 3v - 0.4 v i ol = 0.1 ma, v ccio = 3v - 0.2 v symbol parameter test conditions min. max. units v ccio input source voltage 2.3 2.7 v v ih high level input voltage 1.7 v ccio + 0.3 (1) v v il low level input voltage ?0.3 0.7 v v oh high level output voltage, industrial grade i oh = ?8 ma, v ccio = 2.3v v ccio ? 0.4v - v i oh = ?0.1 ma, v ccio = 2.3v v ccio ? 0.2v - v high level output voltage, q-grade i oh = ?4 ma, v ccio = 2.3v v ccio ? 0.4v - v i oh = ?0.1 ma, v ccio = 2.3v v ccio ? 0.2v - v v ol low level output voltage, industrial grade i ol = 8 ma, v ccio = 2.3v - 0.4 v i ol = 0.1 ma, v ccio = 2.3v - 0.2 v low level output voltage, q-grade i ol = 4 ma, v ccio = 2.3v - 0.4 v i ol = 0.1 ma, v ccio = 2.3v - 0.2 v
xa2c128 coolrunner-ii automotive cpld ds554 (v1.2) june 9, 2009 www.xilinx.com product specification 5 r lvcmos 1.8v dc voltage specifications 1. the v ih max value represents the jedec specification for lvcmos18. the coolrunner-ii input buffer can tolerate up to 3.9v without physical damage. lv c m o s 1.5v dc voltage specifications (1) schmitt trigger input dc voltage specifications ac electrical characteristics over recommended operating conditions symbol parameter test conditions min. max. units v ccio input source voltage 1.7 1.9 v v ih high level input voltage 0.65 x v ccio v ccio + 0.3 (1) v v il low level input voltage ?0.3 0.35 x v ccio v v oh high level output voltage, industrial grade i oh = ?8 ma, v ccio = 1.7v v ccio ? 0.45 - v i oh = ?0.1 ma, v ccio = 1.7v v ccio ? 0.2 - v high level output voltage, q-grade i oh = ?4 ma, v ccio = 1.7v v ccio ? 0.45 - v i oh = ?0.1 ma, v ccio = 1.7v v ccio ? 0.2 - v v ol low level output voltage, industrial grade i ol = 8 ma, v ccio = 1.7v - 0.45 v i ol = 0.1 ma, v ccio = 1.7v - 0.2 v low level output voltage, q-grade i ol = 4 ma, v ccio = 1.7v - 0.45 v i ol = 0.1 ma, v ccio = 1.7v - 0.2 v symbol parameter test conditions min. max. units v ccio input source voltage - 1.4 1.6 v v t+ input hysteresis threshold voltage - 0.5 x v ccio 0.8 x v ccio v v t- -0.2 x v ccio 0.5 x v ccio v v oh high level output voltage, industrial grade i oh = ?8 ma, v ccio = 1.4v v ccio ? 0.45 - v i oh = ?0.1 ma, v ccio = 1.4v v ccio ? 0.2 - v high level output voltage, q-grade i oh = ?4 ma, v ccio = 1.4v v ccio ? 0.45 - v i oh = ?0.1 ma, v ccio = 1.4v v ccio ? 0.2 - v v ol high level output voltage, industrial grade i ol = 8 ma, v ccio = 1.4v - 0.4 v i ol = 0.1 ma, v ccio = 1.4v - 0.2 v high level output voltage, q-grade i ol = 4 ma, v ccio = 1.4v - 0.4 v i ol = 0.1 ma, v ccio = 1.4v - 0.2 v notes: 1. hysteresis used on 1.5v inputs. symbol parameter test conditions min. max. units v ccio input source voltage - 1.4 3.9 v v t+ input hysteresis threshold voltage - 0.5 x v ccio 0.8 x v ccio v v t- -0.2 x v ccio 0.5 x v ccio v symbol parameter -7 -8 units min. max. min. max. t pd1 propagation delay single p-term - 7.0 - 7.0 ns t pd2 propagation delay or array - 7.5 - 7.5 ns t sud direct input register set-up time 4.6 - 4.6 - ns
xa2c128 coolrunner-ii automotive cpld ds554 (v1.2) june 9, 2009 www.xilinx.com product specification 6 r t su1 setup time fast (single p-term) 3.0 - 3.0 - ns t su2 setup time (or array) 3.5 - 3.5 - ns t hd direct input register hold time 0.0 - 0.0 - ns t h hold time (or array or p-term) 0.0 - 0.0 - ns t co clock to output - 5.4 - 5.4 ns f toggle (1) internal toggle rate - 300 - 300 mhz f system1 (2) maximum system frequency - 152 - 152 mhz f system2 (2) maximum system frequency - 141 - 141 mhz f ext1 (3) maximum external frequency - 119 - 119 mhz f ext2 (3) maximum external frequency - 112 - 112 mhz t psud direct input register p-term clock setup time 3.1 - 3.1 - ns t psu1 p-term clock setup time (single p-term) 1.5 - 1.5 - ns t psu2 p-term clock setup time (or array) 2.0 - 2.0 - ns t phd direct input register p-term clock hold time 0.2 - 0.2 - ns t ph p-term clock hold 1.0 - 1.0 - ns t pco p-term clock to output - 7.3 - 7.3 ns t oe /t od global oe to output enable/disable - 7.5 - 7.5 ns t poe /t pod p-term oe to output enable/disable - 8.5 - 8.5 ns t moe /t mod macrocell driven oe to output enable/disable - 9.9 - 9.9 ns t pao p-term set/reset to output valid - 8.1 - 8.1 ns t ao global set/reset to output valid - 7.6 - 7.6 ns t suec register clock enable setup time 3.5 - 3.5 - ns t hec register clock enable hold time 0.0 - 0.0 - ns t cw global clock pulse width high or low 1.6 - 1.6 - ns t aprpw asynchronous preset/reset pulse width (high or low) 7.5 - 7.5 - ns t pcw p-term pulse width high or low 7.5 - 7.5 - ns t dgsu set-up before datagate latch assertion 0.0 - 0.0 - ns t dgh hold to datagate latch assertion 6.0 - 6.0 - ns t dgr datagate recovery to new data - 9.0 9.0 ns t dgw datagate low pulse width 4.0 - 4.0 - ns t cdrsu cdrst setup time before falling edge gclk2 2.0 - 2.0 - ns t cdrh hold time cdrst after falling edge gclk2 0.0 - 0.0 - ns t config (4) configuration time - 350 - 350 us notes: 1. f toggle is the maximum clock frequency to which a t flip-flop can relia bly toggle (see the coolrunner-ii automotive cpld family data sheet). 2. f system1 is the internal operating frequency for a device with 16-bi t resetable binary counter through one p-term per macrocell while f system2 is through the or array (one counter per function block). 3. f ext1 (1/t su1 +t co ) is the maximum external frequency using one p-term while f ext2 is through the or array. 4. typical configuration current during t config is 10 ma. symbol parameter -7 -8 units min. max. min. max.
xa2c128 coolrunner-ii automotive cpld ds554 (v1.2) june 9, 2009 www.xilinx.com product specification 7 r internal timing parameters symbol parameter (1) -7 -8 units min. max. min. max. buffer delays t in input buffer delay - 2.6 - 2.6 ns t din direct data register input delay - 5.3 - 5.3 ns t gck global clock buffer delay - 2.1 - 2.1 ns t gsr global set/reset buffer delay - 3.5 - 3.5 ns t gts global 3-state buffer delay - 3.0 - 3.0 ns t out output buffer delay - 2.6 - 2.6 ns t en output buffer enable/disable delay - 4.5 - 4.5 ns p-term delays t ct control term delay - 1.4 - 1.4 ns t logi1 single p-term delay adder - 1.1 - 1.1 ns t logi2 multiple p-term delay adder - 0.5 - 0.5 ns macrocell delay t pdi input to output valid - 0.7 - 0.7 ns t ldi setup before clock (transparent latch) - 2.5 - 2.5 ns t sui setup before clock 1.4 - 1.4 - ns t hi hold after clock 0.0 - 0.0 - ns t ecsu enable clock setup time 1.6 - 1.6 - ns t echo enable clock hold time 0.0 - 0.0 - ns t coi clock to output valid - 0.7 - 0.7 ns t aoi set/reset to output valid - 1.5 - 1.5 ns feedback delays t f feedback delay - 3.4 - 3.4 ns t oem macrocell to global oe delay - 2.6 - 2.6 ns i/o standard time adder delays 1.5v cmos t hys15 hysteresis input adder - 4.0 - 4.0 ns t out15 output adder - 1.0 - 1.0 ns t slew15 output slew rate adder - 4.0 - 4.0 ns i/o standard time adder delays 1.8v cmos t hys18 hysteresis input adder - 4.0 - 4.0 ns t out18 output adder - 0.0 - 0.0 ns t slew18 output slew rate adder - 4.0 - 4.0 ns
xa2c128 coolrunner-ii automotive cpld ds554 (v1.2) june 9, 2009 www.xilinx.com product specification 8 r switching characteristics figure 2: derating curve for t pd switching test conditions figure 3: ac load circuits i/o standard time adder delays 2.5v cmos t in25 standard input adder - 0.7 - 0.7 ns t hys25 hysteresis input adder - 3.0 - 3.0 ns t out25 output adder - 0.9 - 0.9 ns t slew25 output slew rate adder - 4.0 - 4.0 ns i/o standard time adder delays 3.3v cmos/ttl t in33 standard input adder - 0.6 - 0.6 ns t hys33 hysteresis input adder - 3.0 - 3.0 ns t out33 output adder - 1.4 - 1.4 ns t slew33 output slew rate adder - 4.0 - 4.0 ns notes: 1. 1.5 ns input pin signal rise/fall. internal timing parameters (continued) symbol parameter (1) -7 -8 units min. max. min. max. n u m b er of o u tp u t s s witching 12 4 8 16 4.0 4.4 4. 8 v cc = v ccio = 1. 8 v, 25 o c t pd2 (n s ) 5.0 4.6 4.2 d s 554_02_052109 r 1 v cc c l r 2 device under te s t output t ype lv t t l 33 lv c m o s33 lv c m o s 25 lv c m o s 1 8 lv c m o s 15 r 1 26 8 275 1 88 112.5 150 r 2 2 3 5 275 1 88 112.5 150 c l 3 5 pf 3 5 pf 3 5 pf 3 5 pf 3 5 pf d s 554_0 3 _052109 te s t point note s : 1. c l incl u de s te s t fixt u re s a nd pro b e c a p a cit a nce. 2. 1.5 n s m a xim u m ri s e/f a ll time s on inp u t s .
xa2c128 coolrunner-ii automotive cpld ds554 (v1.2) june 9, 2009 www.xilinx.com product specification 9 r typical i/v output curves 11 figure 4: typical i/v curves for xa2c128 vo (output volts) ds554_04_052109 io (output current ma) 0 0 40 10 50 20 30 60 3.0 2.5 2.0 1.5 1.0 0.5 3.5 3.3v 1.5v 1.8v 2.5v iol pin descriptions function block macro- cell vqg100 cpg132 i/o bank 1113g12 12-f12 1312f22 1411f32 1510e12 169e22 17--- 18--- 19--- 110--- 1118e32 1127d12 1136d22 114-c12 1(gts1) 15 4 c2 2 1(gts0) 16 3 c3 2 21-g21 2214g31 2315h11 2416h21 2517h31 2618j11 27--- 28--- 29--- 210--- 21119j21 212-k11 2(gck0) 13 22 k3 1 2(gck1) 14 23 l2 1 2(cdrst) 15 24 m2 1 2(gck2) 16 27 n2 1 pin descriptions (continued) function block macro- cell vqg100 cpg132 i/o bank
xa2c128 coolrunner-ii automotive cpld ds554 (v1.2) june 9, 2009 www.xilinx.com product specification 10 r 31-b12 3(gts3) 2 2 b2 2 3(gts2) 3 1 a1 2 3(gsr) 4 99 a3 2 3597b42 3696a42 3795c52 38--- 39--- 310--- 31194b52 312 a52 31393c62 31492b62 31591a62 31690c72 4(dge) 1 28 p2 1 42-m31 43-n31 4429p31 4530m41 4632m51 4733n51 48--- 49--- 410--- 41134p51 41235m61 41336n61 41437p61 41539n71 41640m71 pin descriptions (continued) function block macro- cell vqg100 cpg132 i/o bank 5165g132 5266g122 5367f142 54-f132 5568f122 56-e132 5770e122 58--- 59--- 510--- 51171d142 51272d132 51373d122 51474c142 51576b132 516-a132 6164h121 6263h131 6361j131 6460j121 6559k141 6658k131 67--- 68--- 69--- 610--- 6 11 - l14 1 6 12 56 l13 1 6 13 - l12 1 61455m141 615-m131 61654m121 pin descriptions (continued) function block macro- cell vqg100 cpg132 i/o bank
xa2c128 coolrunner-ii automotive cpld ds554 (v1.2) june 9, 2009 www.xilinx.com product specification 11 r 7177c122 7278b122 73-a122 7479c112 7580b112 7681a112 77-c102 78--- 79--- 710--- 71182a102 712-c92 71385a82 71486b82 71587c82 71689b72 pin descriptions (continued) function block macro- cell vqg100 cpg132 i/o bank 81-n141 8253n131 8352p141 8450p121 85-m111 8649n111 87--- 88--- 89--- 810--- 811-p111 81246p101 81344p91 81443m81 81542n81 81641p81 notes: 1. gts = global output enable, gsr = global reset/set, gck = global clock, cdrst = clock divide reset, dge = datagate enable. 2. gck, gsr, and gts pins can also be used for general purpose i/o. pin descriptions (continued) function block macro- cell vqg100 cpg132 i/o bank
xa2c128 coolrunner-ii automotive cpld ds554 (v1.2) june 9, 2009 www.xilinx.com product specification 12 r xa2c128 jtag, power/ground, no c onnect pins and total user i/o ordering information pin type vqg100 (1) cpg132 (1) tck 48 m10 tdi 45 m9 tdo 83 b9 tms 47 n10 v ccaux (jtag supply voltage) 5 d3 power internal (v cc ) 26, 57 p1, k12, a2 power bank 1 i/o (v ccio1 ) 20, 38, 51 j3, p7, g14, p13 power bank 2 i/o (v ccio2 ) 88, 98 a14, c4, a7 ground 21, 25, 31, 62, 69, 75, 84, 100 k2, n1, p4, n9, n12, j14, h14, e14, b14, a9, b3 no connects - l1, l3, m1, n4, c13, b10 total user i/o (including dual function pins) 80 100 notes: 1. pin compatible with all larger and smaller densities except where i/o banking is used. part number pin/ball spacing ja (c/watt) jc (c/watt) package type package body dimensions i/o ind. (i) (1) hi-t (q) xa2c128-7vqg100i 0.5mm 47.5 12.5 very thin quad flat pack; pb-free 14mm x 14mm 80 i xa2c128-8vqg100q 0.5mm 47.5 12.5 very thin quad flat pack; pb-free 14mm x 14mm 80 q XA2C128-7CPG132I 0.5mm 72.4 15.7 chip scale package; pb-free 8mm x 8mm 100 i xa2c128-8cpg132q 0.5mm 72.4 15.7 chip scale package; pb-free 8mm x 8mm 100 q notes: i = industrial (t a = ?40 c to +85 c); q = automotive ( t a = ?40 c to +105 c with t j maximum = +125 c ) . pb- free example: xa2c128 vq g 100 i device speed grade package type pb -free number of pins -7 temperature range
xa2c128 coolrunner-ii automotive cpld ds554 (v1.2) june 9, 2009 www.xilinx.com product specification 13 r device part marking note: due to the small size of chip scale packages, the complete ordering part number cannot be included on the package marking. part marking on chip scale packages by line are: ? line 1 = x (xilinx logo) th en truncated part number ? line 2 = not related to device part number ? line 3 = not related to device part number ? line 4 = package code, speed, operating temperature, three digits not related to device part number. package codes: c6 = cpg132. figure 5: sample package with part marking xc2cxxx tq144 7c device type package speed operating range this line not related to device part number part marking for all non chip scale packages r d s 554_05_052109 figure 6: vqg100 very thin quad flat pack vqg100 top view gnd i/o ( 3 ) vccio2 i/o i/o i/o i/o i/o i/o i/o i/o i/o v ccio2 i/o i/o i/o gnd tdo i/o i/o i/o i/o i/o i/o i/o vcc i/o (2) i/o (5) i/o i/o gnd i/o i/o i/o i/o i/o i/o vccio1 i/o i/o i/o i/o i/o i/o tdi i/o tm s tck i/o i/o gnd i/o i/o i/o i/o i/o gnd i/o i/o i/o i/o i/o i/o gnd i/o i/o i/o i/o vcc i/o i/o i/o i/o i/o vccio1 i/o (1) i/o (1) i/o (1) i/o (1) v aux i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o vccio1 gnd i/o (2) i/o (2) i/o (4) gnd 1 2 3 4 5 6 7 8 9 10 11 12 1 3 14 15 16 17 1 8 19 20 21 22 2 3 24 25 75 74 7 3 72 71 70 69 6 8 67 66 65 64 6 3 62 61 60 59 5 8 57 56 55 54 5 3 52 51 26 27 2 8 29 3 0 3 1 3 2 33 3 4 3 5 3 6 3 7 38 3 9 40 41 42 4 3 44 45 46 47 4 8 49 50 100 99 9 8 97 96 95 94 9 3 92 91 90 8 9 88 8 7 8 6 8 5 8 4 83 8 2 8 1 8 0 79 7 8 77 76 (1) - glo ba l o u tp u t en ab le (2) - glo ba l clock ( 3 ) - glo ba l s et/re s et (4) - clock divide re s et (5) - d a t a g a te d s 554_06_052109
xa2c128 coolrunner-ii automotive cpld ds554 (v1.2) june 9, 2009 www.xilinx.com product specification 14 r coolrunner-ii automotive requ irements and recommendations requirements the following requirements are for all automotive applica- tions: 1. use a monotonic, fast ramp power supply to power up coolrunner-ii. a v cc ramp time of less than 1 ms is required. 2. do not float i/o pins during device operation. floating i/o pins can increase i cc as input buffers will draw 1-2 ma per floating input. in addition, when i/o pins are floated, noise can propagate to the center of the cpld. i/o pins should be appropriately terminated with bus-hold or pull-up. unused i/os can also be configured as c gnd (programmable gnd). 3. do not drive i/o pins without v cc /v ccio powered. 4. sink current when drivi ng leds. because all xilinx cplds have n-channel pull-down transistors on outputs, it is required that an led anode is sourced through a resistor externally to v cc . consequently, this will give the brightest solution. 5. avoid pull-down resistors. always use external pull-up resistors if external termination is required. this is because the coolrunner-ii automotive cpld, which includes some i/o driving circuits beyond the input and output buffers, may have contention with external pull- down resistors, and, cons equently, the i/o will not switch as expected. figure 7: cp132 chip scale package cpg1 3 2 bottom view p n m l k j h g f e d c b a 1 2 3 4 5 6 7 8 9 10 11 12 1 3 14 vcc vccio1 vccio1 gnd i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o(5) i/o i/o vaux i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o vccio1 i/o i/o i/o i/o i/o gnd i/o i/o i/o i/o i/o gnd i/o i/o i/o vccio1 i/o gnd i/o i/o i/o i/o(2) vcc i/o gnd nc i/o nc i/o i/o i/o(2) i/o(1) vccio2 i/o i/o i/o( 3 ) i/o i/o i/o gnd i/o i/o i/o vccio2 vcc i/o i/o i/o i/o gnd i/o i/o i/o tdo nc i/o i/o gnd i/o(1) i/o i/o nc vccio2 i/o(1) i/o i/o i/o i/o i/o i/o i/o i/o i/o(1) nc i/o i/o i/o i/o i/o i/o i/o tdi tck i/o i/o i/o i/o(4) gnd i/o i/o nc i/o i/o i/o i/o gnd tm s i/o gnd i/o i/o(2) (1) - glo ba l o u tp u t en ab le (2) - glo ba l clock ( 3 ) - glo ba l s et/re s et (4) - clock divide re s et (5) - d a t a gate en ab le d s 554_07_052109
xa2c128 coolrunner-ii automotive cpld ds554 (v1.2) june 9, 2009 www.xilinx.com product specification 15 r 6. do not drive i/os pins above the v ccio assigned to its i/o bank. a. the current flow can go into v ccio and affect a user voltage regulator. b. it can also increase undesired leakage current associated with the device. c. if done for too long, it can reduce the life of the device. 7. do not rely on the i/o states before the cpld configures. during power up, the cpld i/os may be affected by internal or external signals. 8. use a voltage regulator which can provide sufficient current during device power up. as a rule of thumb, the regulator needs to provide at least three times the peak current while powering up a cpld in order to guarantee the cpld can configure successfully. 9. ensure external jtag terminations for tms, tck, tdi, tdo should comply with the ieee 1149.1. all xilinx cplds have internal weak pull-ups on tdi, tms, and tck. 10. attach all cpld v cc and gnd pins in order to have necessary power and ground supplies around the cpld. 11. decouple all v cc and v ccio pins with capacitors of 0.01 f and 0.1 f closest to the pins for each v cc /v ccio -gnd pair. 12. configure i/os properly. coolrunner-ii automotive cplds have i/o banks; therefore, signals must be assigned to appropriate banks (lvcmos33, lv c m o s 1 8 ? ) recommendations the following recommendations are for all automotive appli- cations. 1. use strict synchronous design (only one clocking event) if possible. a synchronous system is more robust than an asynchronous one. 2. include jtag stakes on the pcb. jtag stakes can be used to test the part on the pcb. they add benefit in reprogramming part on the pcb, inspecting chip internals with intest, identifying stuck pins, and inspecting programming patterns (if not secured). 3. coolrunner-ii automotive cplds work with any power sequence, but it is preferable to power the v cci (internal v cc ) before the v ccio for the applications in which any glitches from device i/os are unwanted. 4. do not disregard report file warnings. software identifies potent ial problems when compiling, so the report file is worth inspecting to see exactly how your design is mapped onto the logic. 5. understand the timing report. this report file provides a speed summary along with warnings. read the timing file (*.tim) carefully. analyze key signal chains to determine limits to given clock(s) based on logic analysis. 6. review fitter report equations. equations can be shown in abel-like format, or can also be displayed in verilog or vhdl formats. the fitter report also includes switch settings th at are very informative of other device behaviors. 7. let design software define pinouts if possible. xilinx cpld software works best when it selects the i/o pins and manages resources for users. it can spread signals around and improve pin-locking. if users must define pins, plan resources in advance. 8. perform a post-fit simulation for all speeds to identify any possible problems (such as race conditions) that might occur when fast-speed silicon is used instead of slow-speed silicon. 9. distribute ssos (simultaneously switching outputs) evenly around the cpld to reduce switching noise. 10. terminate high speed outputs to eliminate noise caused by very fast rising/falling edges. additional information additional information is available fo r the following coolrunner-ii topics: ? xapp784 : bulletproof cpld design practices ? xapp375 : timing model ? xapp376 : logic engine ? xapp378 : advanced features ? xapp382 : i/o characteristics ? xapp389 : powering coolrunner-ii ? xapp399 : assigning vref pins these and other application notes can be accessed at: coolrunner-ii d ocumentation package specifications can be accessed at: device package s
xa2c128 coolrunner-ii automotive cpld ds554 (v1.2) june 9, 2009 www.xilinx.com product specification 16 r revision history the following table shows the revision history for this document. notice of disclaimer the xilinx hardware fpga and cpld devices referred to herein (?products?) are subject to the terms and conditions of the xilinx limited warranty which can be viewed at http://www.xilinx.com/warranty.htm . this limited warranty does not extend to any use of products in an application or environment that is not with in the specifications stated in the xilinx data sheet. all specifications are subject to change without notice. products are not designed or intended to be fail-safe or for use in any appl ication requiring fail-safe performance, such as life-support or safety devices or systems, or any other application that invokes the potential risks of death, personal injury, or property or environmental damage (?critical applications?). use of products in critical applicat ions is at the sole risk of customer, subject to applicable laws and regulations. automotive applications disclaimer xilinx products are not designed or intended to be fail-safe, or for use in any application requiring fail-safe performance, such as appl ications related to: (i) the deployment of airbags, (ii) control of a vehicle, unless there is a fail-safe or redundancy feature (which does not include use of software in the xilinx device to implement the redundancy) and a warning signal upon failure to the operator, or (iii) uses that could lead to death or personal injury. customer assumes the sole risk and liability of any use of xilinx products in such applications. date version revision 10/31/06 1.0 initial xilinx release. 05/05/07 1.1 change to v ih specification for 3.3v, 2.5v and 1.8v lvcmos. corrections to t sui , t ecsu , t f , and t oem for the -7 speed grade. values now match the software. there were no changes to silicon or characterization. 06/09/09 1.2 corrected xa2c128-8vqg100q part number in ordering information .

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